Leveraging AI and ML Methods in Chip Design
In this course, we cover reasons for incorporation of AI and ML in modern chip design methods and design automation tools. The most important reason: the inexorable “Moore’s Law” need to scale cost, schedule efficiency, and IC product quality in terms of key metrics such as speed, energy efficiency, and manufacturing cost. We explain how AI and machine learning provide new levers for chip design: adding human-like intelligence to search and optimization, and leveraging collected data from past design iterations and experiences. Benefits include the lowering of expertise barriers, and the augmentation – and, reduction – of human engineering effort.
Brought to you by IEEE Educational Activities in partnership with IEEE Future Directions.
What you will learn:
Part 1: Why AI and ML in IC Design and EDA
In Part 1, we will cover some introductory concepts related to today’s high level of interest in application of AI/ML to IC design and EDA. At the end of this session, you will be able to:
- Describe why AI/ML is crucial to improving designer productivity and design quality
- Describe how optimization, automation and AI/ML advance IC design and EDA
- Describe the basic resource constraints that the IC design process must live with
Part 2: Applications and Use Cases
In Part 2, we will cover several driving applications and use cases for AI/ML in IC design and EDA. At the end of this session, you will be able to:
- Describe key IC design and EDA applications, along with usage scenarios, where AI/ML is expected to yield benefits
- Describe the key types of AI/ML goals in the design process: Mechanization, Orchestration, and Modeling and Prediction
- Describe the roles that designers, EDA suppliers, AI/ML experts and academic researchers play in the deployment of future methods
Part 3: Important Techniques
In Part 3, we will introduce the most relevant AI/ML techniques. At the end of this session, you’ll be able to:
- Describe the differences among supervised, unsupervised and reinforcement learning methods
- Describe emerging opportunities for Generative AI, particularly the use of Large Language Models, in design and EDA
This course is part of the following Course Program:
AI and ML in Chip Design
Courses included in this program:
Who Should Attend: IC Designers, IC Design Project Managers, IC CAD Integrators, EDA Researchers, Developers, and Educators, AI and ML Researchers, Developers, and Educators, R&D Program Managers
Instructor
Andrew B. Kahng
Andrew B. Kahng is Distinguished Professor of CSE and ECE and holder of the endowed chair in high-performance computing at the University of California at San Diego. He received the A.B. degree in applied mathematics (physics) from Harvard College, and the M.S. and Ph.D. degrees in computer science from UC San Diego. From 1989 to 2000, he was on the UCLA computer science faculty before moving to UC San Diego in 2001. He was visiting scientist at Cadence Design Systems (1995-97) and founder/CTO at Blaze DFM (2004-06). He is coauthor of 3 books and over 500 journal and conference papers, holds 35 issued U.S. patents, and is a Fellow of IEEE and of ACM. He was the 2019 Ho-Am Prize laureate in Engineering. From 2000-2016 he served as international chair/co-chair of the International Technology Roadmap for Semiconductors (ITRS) Design and System Drivers working groups. He has served as general chair of IEEE-sponsored conferences such as the Design Automation Conference, the International Symposium on Physical Design, and the Workshop on Machine Learning. He has also served on the editorial boards of IEEE Transactions on VLSI, IEEE Transactions on Circuits and Systems I, and IEEE Design and Test (where he contributes the regular column, “The Road Ahead”).
Publication Year: 2024
ISBN: 978-1-7281-7870-7