Artificial Intelligence and Machine Learning in Chip Design

  • Online

Day 1: 13 August 2024 12-2pm ET

Day 2: 14 August 2024 12-2pm ET

Join us as we delve into the transformative realm of Artificial Intelligence (AI) and Machine Learning (ML) in chip design and Electronic Design Automation (EDA) with our subject matter expert, Professor Andrew B. Kahng.

In today's fast-paced technological landscape, AI and ML techniques are revolutionizing chip design methodologies. Integrated-circuit (IC) chip companies and engineers have unprecedented opportunities to use these technologies to enhance product quality across crucial dimensions such as speed, energy efficiency, and cost. This, in turn, allows for meeting goals with reduced engineering resources and accelerated time-to-market.

This comprehensive two-day virtual training session will equip engineers with the:

  • Essential knowledge to leverage AI and ML effectively in chip design and EDA,
  • Understanding of the rationale behind these technological shifts to identifying high-value applications and selecting relevant AI and ML technologies, and
  • Insights into optimizing design methods and preparing for the future of chip design.

Attendees of the live virtual training will also have the opportunity for first-hand interaction with Professor Kahng and ask him questions during the interactive question and answer portion of the training.

Successful completion of this training and assessment will award attendees an IEEE Certificate of Completion bearing professional development hours (PDHs) and continuing education units (CEUs).

Don't miss this opportunity to communicate directly with a leader in the industry! Register now to secure your spot in this enlightening training session. 

Upon purchase of this event, you will receive a confirmation email (including the URL link to access the event).


Andrew B. Kahng

Andrew B. Kahng is Distinguished Professor of CSE and ECE and holder of the endowed chair in high-performance computing at the University of California at San Diego. He received the A.B. degree in applied mathematics (physics) from Harvard College, and the M.S. and Ph.D. degrees in computer science from UC San Diego. From 1989 to 2000, he was on the UCLA computer science faculty before moving to UC San Diego in 2001.  He was visiting scientist at Cadence Design Systems (1995-97) and founder/CTO at Blaze DFM (2004-06). He is coauthor of 3 books and over 500 journal and conference papers, holds 35 issued U.S. patents, and is a Fellow of IEEE and of ACM. He was the 2019 Ho-Am Prize laureate in Engineering. From 2000-2016 he served as international chair/co-chair of the International Technology Roadmap for Semiconductors (ITRS) Design and System Drivers working groups. He has served as general chair of IEEE-sponsored conferences such as the Design Automation Conference, the International Symposium on Physical Design, and the Workshop on Machine Learning. He has also served on the editorial boards of IEEE Transactions on VLSI, IEEE Transactions on Circuits and Systems I, and IEEE Design and Test (where he contributes the regular column, “The Road Ahead”).

Publication Year: 2024

Artificial Intelligence and Machine Learning in Chip Design
  • Course Provider: Educational Activities
  • Course Number: EDP728
  • Duration (Hours): 4
  • Credits: None