Integrated Circuit Digital Design Methodology
Course content reaffirmed: 06/2015--A design methodology for sizing and determining delays in logic paths will be developed that will be used throughout the design cycle. One of the key items in sizing and optimizing the logic path is called fanout which will be the main focuses of this tutorial. We will first determine what fanout is and how it relates to the gain (output capacitance vs. input capacitance) of an inverter and a complete logic path. Then, a delay equation for calculating the delay through any logic path based on fanout will be created to aid in quickly calculating the initial timing and sizing of the logic gates. Timing and sizing calculations will always be related to an inverter, so we will review how to convert a NAND and NOR gate drive strength to an equivalent inverter to be used in the delay equation. A key question that will always arise throughout a design will be: what is the optimum fanout when we have a very small initial stage in a logic path that must eventually drive a large capacitance? In another words, how many gain stages should we use and what size should each stage be. To answer this, we will create a graph that will tell us the optimum fanout that we should always use and thus standardize the delay per stage. Standardizing fanout will eliminate many variations within our design and allow for all logic paths to track over process, temperature and voltage variations. This is a very important design methodology in improving the quality of our design and helping to insure that it works the first time.
What you will learn:
- Discuss how to follow a design methodology / approach for sizing and determining delays in logic paths
- Review equating all types of logic gates to a standard inverter with equal drive strengths and delay time
- Examine keeping ratio of gate size to its load the same for each gate used in the logic path - Fanout
Related courses:
Who should attend: Electrical engineer, Design engineer, Product engineer, Lead engineer, Project engineer, Manufacturing engineer
Instructor
Doug Sheppard
Doug Sheppard has 33 years experience designing and developing integrated circuits. He is currently President, Owner and founder of Valence, Inc (www.valence-inc.com) that was started in 1993. Valence specializes in digital integrated circuit design with a main focus on memories. Some of the key products are embedded libraries, custom memories & memory compiler products.
Publication Year: 2009
ISBN: 978-1-4244-3002-4