AI Applications in Semiconductor Packaging
Live Virtual Training--Available On Demand
Event Date: Wednesday, 12 November 2025 10 am–12 pm ET
This two-hour live training explores how AI is transforming semiconductor packaging reliability, contrasting traditional methods with advanced techniques for performance prediction, failure analysis, and lifecycle optimization.
Learners will:
- Compare traditional and AI-driven approaches to semiconductor packaging reliability, gaining insight into how artificial intelligence transforms performance prediction and failure analysis.
- Understand key categories of AI, including machine learning (ML), deep learning, and generative AI—with distinctions between supervised, unsupervised, and generative models.
- Explore neural networks for Semiconductor Packaging, specifically their components, including activation functions and neuron models, through analogies to human cognition and decision-making.
- Discover select AI/ML techniques such as Support Vector Machines, K-Means clustering, Self-Organizing Maps, and Long-Short-Term Memory networks, and how they apply to packaging reliability.
- Apply AI methods to real-world challenges in Semiconductor Packaging, including anomaly detection, machine state assessment, digital twin modeling, and forecasting the timing of future failures.
Who Should Attend: Semiconductor Packaging Engineers, AI/ML Engineers and Data Scientists, Systems Engineers, Reliability Engineers, Sustainability Leads in Electronics Manufacturing, Quality Assurance Specialists, Innovation Leads and CTOs, Academic Researchers and Graduate Students
This live training event is part of the 2025 IEEE eLearning Library. Access to the live training and future on-demand content is available via IEEE Xplore and the IEEE Learning Network to customers who purchase the training or the full IEEE eLearning Library collection.
Instructor
Dr. Pradeep Lall
Dr. Pradeep Lall, IEEE Fellow and MacFarlane Endowed Distinguished Professor at Auburn University, is a globally recognized leader in electronics packaging and reliability. As Director of the Auburn University Electronics Packaging Research Institute, he brings deep expertise shaped by prior work at Motorola and over 1000 published journal and conference papers, along with two books and 15 book chapters. He holds a Ph.D. in Mechanical Engineering from the University of Maryland and an MBA from Northwestern University, and has earned more than 50 best-paper awards plus major honors from IEEE, ASME, SMTA, SEMI, and NSF for his groundbreaking contributions to electronics manufacturing and design.
Publication Year: 2025