Dual Port SRAM: Memory Architecture

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The sub-blocks of the dual port memory architecture is presented in the course with a key focus on the path from the array bit lines to the data pins for both the read and write. A memory can have many possibilities of how the bits and bits per word is configured which is based on the number of rows and columns in the array. All of the key blocks required to decode the columns, sense the data, select and decode the sense amp and drive the Data Out pin for a read from the bit lines are discussed. The write path from the Data In pin up through the column decode and write select circuitry is also presented.

What you will learn:

  • Review all of the key blocks required to decode the columns, sense the data, select and decode the sense amp and drive the Data Out pin for a read from the bit lines are discussed

Related courses:

Who should attend: Electrical engineer, Design engineer, Product engineer, Lead engineer, Project engineer, Manufacturing engineer

Instructor

Doug Sheppard

Doug Sheppard Photo

Doug Sheppard has 33 years experience designing and developing integrated circuits. He is currently President, Owner and founder of Valence, Inc (www.valence-inc.com) that was started in 1993. Valence specializes in digital integrated circuit design with a main focus on memories. Some of the key products are embedded libraries, custom memories & memory compiler products.

Publication Year: 2011

ISBN:978-1-61284-515-9


Dual Port SRAM:  Memory Architecture
  • Course Provider: Educational Activities
  • Course Number: EDP224
  • Duration (Hours): 1
  • Credits: 0.1 CEU/ 1 PDH